module Count_Clk(
  input          clock,
  input          reset,
  output         io_Data_in,
  output [7:0]   io_count_clk_in,
  output [7:0]   io_count_clk_delay,
  output [7:0]   io_count_clk_enable,
  output [7:0]   io_count_clk_out,
  input  [209:0] io_Data,
  input  [2:0]   io_stateReg
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] count_clk_in; // @[PUF_Core.scala 132:36]
  reg [7:0] count_clk_delay; // @[PUF_Core.scala 133:36]
  reg [7:0] count_clk_enable; // @[PUF_Core.scala 134:36]
  reg [7:0] count_clk_out; // @[PUF_Core.scala 135:36]
  wire [209:0] _the_data_in_T = io_Data >> count_clk_in; // @[PUF_Core.scala 138:35]
  wire [7:0] _count_clk_in_T_1 = count_clk_in + 8'h1; // @[PUF_Core.scala 141:42]
  wire [7:0] _count_clk_delay_T_1 = count_clk_delay + 8'h1; // @[PUF_Core.scala 147:45]
  wire [7:0] _count_clk_enable_T_1 = count_clk_enable + 8'h1; // @[PUF_Core.scala 154:50]
  wire [7:0] _count_clk_out_T_1 = count_clk_out + 8'h1; // @[PUF_Core.scala 161:43]
  assign io_Data_in = _the_data_in_T[0]; // @[PUF_Core.scala 138:52]
  assign io_count_clk_in = count_clk_in; // @[PUF_Core.scala 168:25]
  assign io_count_clk_delay = count_clk_delay; // @[PUF_Core.scala 169:25]
  assign io_count_clk_enable = count_clk_enable; // @[PUF_Core.scala 170:25]
  assign io_count_clk_out = count_clk_out; // @[PUF_Core.scala 171:25]
  always @(posedge clock) begin
    if (reset) begin // @[PUF_Core.scala 132:36]
      count_clk_in <= 8'h0; // @[PUF_Core.scala 132:36]
    end else if (io_stateReg == 3'h1) begin // @[PUF_Core.scala 140:36]
      count_clk_in <= _count_clk_in_T_1; // @[PUF_Core.scala 141:25]
    end else begin
      count_clk_in <= 8'h0; // @[PUF_Core.scala 143:25]
    end
    if (reset) begin // @[PUF_Core.scala 133:36]
      count_clk_delay <= 8'h0; // @[PUF_Core.scala 133:36]
    end else if (io_stateReg == 3'h2) begin // @[PUF_Core.scala 146:36]
      count_clk_delay <= _count_clk_delay_T_1; // @[PUF_Core.scala 147:25]
    end else begin
      count_clk_delay <= 8'h0; // @[PUF_Core.scala 150:25]
    end
    if (reset) begin // @[PUF_Core.scala 134:36]
      count_clk_enable <= 8'h0; // @[PUF_Core.scala 134:36]
    end else if (io_stateReg == 3'h3) begin // @[PUF_Core.scala 153:37]
      count_clk_enable <= _count_clk_enable_T_1; // @[PUF_Core.scala 154:29]
    end else begin
      count_clk_enable <= 8'h0; // @[PUF_Core.scala 157:29]
    end
    if (reset) begin // @[PUF_Core.scala 135:36]
      count_clk_out <= 8'h0; // @[PUF_Core.scala 135:36]
    end else if (io_stateReg == 3'h4) begin // @[PUF_Core.scala 160:37]
      count_clk_out <= _count_clk_out_T_1; // @[PUF_Core.scala 161:25]
    end else begin
      count_clk_out <= 8'h0; // @[PUF_Core.scala 164:25]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  count_clk_in = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  count_clk_delay = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  count_clk_enable = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  count_clk_out = _RAND_3[7:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PUF_Core(
  input   clock,
  input   reset,
  output  io_out_Data_in,
  output  io_out_Ena_in,
  output  io_out_Clk_in,
  output  io_out_Ena_out,
  output  io_out_Clk_out,
  input   io_clk_Clk
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  M_Count_Clk_clock; // @[PUF_Core.scala 50:39]
  wire  M_Count_Clk_reset; // @[PUF_Core.scala 50:39]
  wire  M_Count_Clk_io_Data_in; // @[PUF_Core.scala 50:39]
  wire [7:0] M_Count_Clk_io_count_clk_in; // @[PUF_Core.scala 50:39]
  wire [7:0] M_Count_Clk_io_count_clk_delay; // @[PUF_Core.scala 50:39]
  wire [7:0] M_Count_Clk_io_count_clk_enable; // @[PUF_Core.scala 50:39]
  wire [7:0] M_Count_Clk_io_count_clk_out; // @[PUF_Core.scala 50:39]
  wire [209:0] M_Count_Clk_io_Data; // @[PUF_Core.scala 50:39]
  wire [2:0] M_Count_Clk_io_stateReg; // @[PUF_Core.scala 50:39]
  reg  the_ena_out; // @[PUF_Core.scala 18:32]
  reg  io_out_Ena_out_REG; // @[PUF_Core.scala 25:36]
  wire [7:0] count_clk_in = M_Count_Clk_io_count_clk_in;
  wire  trigger_delay = count_clk_in == 8'hd2; // @[PUF_Core.scala 41:44]
  wire [7:0] count_clk_delay = M_Count_Clk_io_count_clk_delay;
  wire  trigger_enable = count_clk_delay == 8'h4; // @[PUF_Core.scala 42:47]
  wire [7:0] count_clk_enable = M_Count_Clk_io_count_clk_enable;
  wire  trigger_output = count_clk_enable == 8'h2; // @[PUF_Core.scala 43:48]
  wire [7:0] _trigger_idle_T_1 = 8'h80 - 8'h2; // @[PUF_Core.scala 44:61]
  wire [7:0] count_clk_out = M_Count_Clk_io_count_clk_out;
  wire  trigger_idle = count_clk_out == _trigger_idle_T_1; // @[PUF_Core.scala 44:45]
  reg [2:0] stateReg; // @[PUF_Core.scala 48:32]
  wire  _T = stateReg == 3'h1; // @[PUF_Core.scala 60:20]
  wire  _T_1 = stateReg == 3'h2; // @[PUF_Core.scala 66:25]
  wire  _T_2 = stateReg == 3'h3; // @[PUF_Core.scala 72:25]
  wire  _T_3 = stateReg == 3'h4; // @[PUF_Core.scala 78:25]
  wire  _GEN_3 = stateReg == 3'h3 | _T_3; // @[PUF_Core.scala 72:39 PUF_Core.scala 74:25]
  wire  _GEN_4 = stateReg == 3'h3 ? 1'h0 : _T_3; // @[PUF_Core.scala 72:39 PUF_Core.scala 75:25]
  wire  _GEN_5 = stateReg == 3'h2 | _T_2; // @[PUF_Core.scala 66:38 PUF_Core.scala 67:25]
  wire  _GEN_6 = stateReg == 3'h2 ? 1'h0 : _GEN_3; // @[PUF_Core.scala 66:38 PUF_Core.scala 68:25]
  wire  _GEN_7 = stateReg == 3'h2 ? 1'h0 : _GEN_4; // @[PUF_Core.scala 66:38 PUF_Core.scala 69:25]
  wire [2:0] _GEN_13 = trigger_output ? 3'h4 : stateReg; // @[PUF_Core.scala 103:32 PUF_Core.scala 104:25 PUF_Core.scala 48:32]
  wire [2:0] _GEN_14 = trigger_idle ? 3'h0 : stateReg; // @[PUF_Core.scala 108:30 PUF_Core.scala 109:25 PUF_Core.scala 48:32]
  wire [2:0] _GEN_16 = _T_3 ? _GEN_14 : 3'h1; // @[PUF_Core.scala 107:38]
  Count_Clk M_Count_Clk ( // @[PUF_Core.scala 50:39]
    .clock(M_Count_Clk_clock),
    .reset(M_Count_Clk_reset),
    .io_Data_in(M_Count_Clk_io_Data_in),
    .io_count_clk_in(M_Count_Clk_io_count_clk_in),
    .io_count_clk_delay(M_Count_Clk_io_count_clk_delay),
    .io_count_clk_enable(M_Count_Clk_io_count_clk_enable),
    .io_count_clk_out(M_Count_Clk_io_count_clk_out),
    .io_Data(M_Count_Clk_io_Data),
    .io_stateReg(M_Count_Clk_io_stateReg)
  );
  assign io_out_Data_in = M_Count_Clk_io_Data_in; // @[PUF_Core.scala 21:33 PUF_Core.scala 58:29]
  assign io_out_Ena_in = stateReg == 3'h1 ? 1'h0 : _GEN_5; // @[PUF_Core.scala 60:33 PUF_Core.scala 61:25]
  assign io_out_Clk_in = stateReg == 3'h1 | _GEN_7; // @[PUF_Core.scala 60:33 PUF_Core.scala 63:25]
  assign io_out_Ena_out = io_out_Ena_out_REG; // @[PUF_Core.scala 25:25]
  assign io_out_Clk_out = stateReg == 3'h1 ? 1'h0 : _GEN_6; // @[PUF_Core.scala 60:33 PUF_Core.scala 62:25]
  assign M_Count_Clk_clock = io_clk_Clk; // @[PUF_Core.scala 51:29]
  assign M_Count_Clk_reset = reset;
  assign M_Count_Clk_io_Data = 210'h2aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa; // @[PUF_Core.scala 52:29]
  assign M_Count_Clk_io_stateReg = stateReg; // @[PUF_Core.scala 53:29]
  always @(posedge clock) begin
    if (stateReg == 3'h1) begin // @[PUF_Core.scala 60:33]
      the_ena_out <= 1'h0; // @[PUF_Core.scala 62:25]
    end else if (stateReg == 3'h2) begin // @[PUF_Core.scala 66:38]
      the_ena_out <= 1'h0; // @[PUF_Core.scala 68:25]
    end else begin
      the_ena_out <= _GEN_3;
    end
    io_out_Ena_out_REG <= the_ena_out; // @[PUF_Core.scala 25:36]
    if (reset) begin // @[PUF_Core.scala 48:32]
      stateReg <= 3'h0; // @[PUF_Core.scala 48:32]
    end else if (_T) begin // @[PUF_Core.scala 92:33]
      if (trigger_delay) begin // @[PUF_Core.scala 93:31]
        stateReg <= 3'h2; // @[PUF_Core.scala 94:25]
      end
    end else if (_T_1) begin // @[PUF_Core.scala 97:38]
      if (trigger_enable) begin // @[PUF_Core.scala 98:31]
        stateReg <= 3'h3; // @[PUF_Core.scala 99:25]
      end
    end else if (_T_2) begin // @[PUF_Core.scala 102:38]
      stateReg <= _GEN_13;
    end else begin
      stateReg <= _GEN_16;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  the_ena_out = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  io_out_Ena_out_REG = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  stateReg = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Clk_Divider(
  input   clock,
  input   reset,
  output  io_clk_out
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  the_clk; // @[Clk_Divider.scala 14:28]
  assign io_clk_out = the_clk; // @[Clk_Divider.scala 17:29]
  always @(posedge clock) begin
    if (reset) begin // @[Clk_Divider.scala 14:28]
      the_clk <= 1'h0; // @[Clk_Divider.scala 14:28]
    end else begin
      the_clk <= ~the_clk; // @[Clk_Divider.scala 15:17]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  the_clk = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module core(
  input   clock,
  input   reset,
  output  io_out_Data_in,
  output  io_out_Ena_in,
  output  io_out_Clk_in,
  output  io_out_Ena_out,
  output  io_out_Clk_out,
  output  io_out_Clk
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  M_PUF_Core_clock; // @[PUF_Top.scala 34:35]
  wire  M_PUF_Core_reset; // @[PUF_Top.scala 34:35]
  wire  M_PUF_Core_io_out_Data_in; // @[PUF_Top.scala 34:35]
  wire  M_PUF_Core_io_out_Ena_in; // @[PUF_Top.scala 34:35]
  wire  M_PUF_Core_io_out_Clk_in; // @[PUF_Top.scala 34:35]
  wire  M_PUF_Core_io_out_Ena_out; // @[PUF_Top.scala 34:35]
  wire  M_PUF_Core_io_out_Clk_out; // @[PUF_Top.scala 34:35]
  wire  M_PUF_Core_io_clk_Clk; // @[PUF_Top.scala 34:35]
  wire  the_clock_M_Clk_Divider_clock; // @[Clk_Divider.scala 23:35]
  wire  the_clock_M_Clk_Divider_reset; // @[Clk_Divider.scala 23:35]
  wire  the_clock_M_Clk_Divider_io_clk_out; // @[Clk_Divider.scala 23:35]
  wire  the_clock_reverse = the_clock_M_Clk_Divider_io_clk_out ? 1'h0 : 1'h1; // @[PUF_Top.scala 38:72]
  reg  the_ena_in; // @[PUF_Top.scala 50:40]
  reg  the_clk_in; // @[PUF_Top.scala 51:40]
  reg  io_out_Data_in_REG; // @[PUF_Top.scala 54:40]
  reg  io_out_Ena_out_REG; // @[PUF_Top.scala 56:40]
  reg  io_out_Clk_out_REG; // @[PUF_Top.scala 58:40]
  reg  io_out_Clk_REG; // @[PUF_Top.scala 59:64]
  reg  io_out_Clk_REG_1; // @[PUF_Top.scala 59:56]
  reg  io_out_Clk_REG_2; // @[PUF_Top.scala 59:48]
  reg  io_out_Clk_REG_3; // @[PUF_Top.scala 59:40]
  PUF_Core M_PUF_Core ( // @[PUF_Top.scala 34:35]
    .clock(M_PUF_Core_clock),
    .reset(M_PUF_Core_reset),
    .io_out_Data_in(M_PUF_Core_io_out_Data_in),
    .io_out_Ena_in(M_PUF_Core_io_out_Ena_in),
    .io_out_Clk_in(M_PUF_Core_io_out_Clk_in),
    .io_out_Ena_out(M_PUF_Core_io_out_Ena_out),
    .io_out_Clk_out(M_PUF_Core_io_out_Clk_out),
    .io_clk_Clk(M_PUF_Core_io_clk_Clk)
  );
  Clk_Divider the_clock_M_Clk_Divider ( // @[Clk_Divider.scala 23:35]
    .clock(the_clock_M_Clk_Divider_clock),
    .reset(the_clock_M_Clk_Divider_reset),
    .io_clk_out(the_clock_M_Clk_Divider_io_clk_out)
  );
  assign io_out_Data_in = io_out_Data_in_REG; // @[PUF_Top.scala 54:29]
  assign io_out_Ena_in = the_ena_in; // @[PUF_Top.scala 55:29]
  assign io_out_Clk_in = the_clk_in; // @[PUF_Top.scala 57:29]
  assign io_out_Ena_out = io_out_Ena_out_REG; // @[PUF_Top.scala 56:29]
  assign io_out_Clk_out = io_out_Clk_out_REG; // @[PUF_Top.scala 58:29]
  assign io_out_Clk = io_out_Clk_REG_3; // @[PUF_Top.scala 59:29]
  assign M_PUF_Core_clock = clock;
  assign M_PUF_Core_reset = reset;
  assign M_PUF_Core_io_clk_Clk = the_clock_M_Clk_Divider_io_clk_out ? 1'h0 : 1'h1; // @[PUF_Top.scala 38:72]
  assign the_clock_M_Clk_Divider_clock = clock;
  assign the_clock_M_Clk_Divider_reset = reset;
  always @(posedge clock) begin
    the_ena_in <= M_PUF_Core_io_out_Ena_in; // @[PUF_Top.scala 50:40]
    the_clk_in <= M_PUF_Core_io_out_Clk_in & the_clock_M_Clk_Divider_io_clk_out; // @[PUF_Top.scala 51:66]
    io_out_Data_in_REG <= M_PUF_Core_io_out_Data_in; // @[PUF_Top.scala 54:40]
    io_out_Ena_out_REG <= M_PUF_Core_io_out_Ena_out; // @[PUF_Top.scala 56:40]
    io_out_Clk_out_REG <= M_PUF_Core_io_out_Clk_out & the_clock_reverse; // @[PUF_Top.scala 58:67]
    io_out_Clk_REG <= the_ena_in; // @[PUF_Top.scala 59:64]
    io_out_Clk_REG_1 <= io_out_Clk_REG; // @[PUF_Top.scala 59:56]
    io_out_Clk_REG_2 <= io_out_Clk_REG_1; // @[PUF_Top.scala 59:48]
    io_out_Clk_REG_3 <= io_out_Clk_REG_2; // @[PUF_Top.scala 59:40]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  the_ena_in = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  the_clk_in = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  io_out_Data_in_REG = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  io_out_Ena_out_REG = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  io_out_Clk_out_REG = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  io_out_Clk_REG = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  io_out_Clk_REG_1 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  io_out_Clk_REG_2 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  io_out_Clk_REG_3 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module top(
  input   clock,
  input   reset,
  output  io_out_Data_in,
  output  io_out_Ena_in,
  output  io_out_Clk_in,
  output  io_out_Ena_out,
  output  io_out_Clk_out,
  output  io_out_Clk
);
  wire  M_Core_clock; // @[PUF_Top.scala 16:35]
  wire  M_Core_reset; // @[PUF_Top.scala 16:35]
  wire  M_Core_io_out_Data_in; // @[PUF_Top.scala 16:35]
  wire  M_Core_io_out_Ena_in; // @[PUF_Top.scala 16:35]
  wire  M_Core_io_out_Clk_in; // @[PUF_Top.scala 16:35]
  wire  M_Core_io_out_Ena_out; // @[PUF_Top.scala 16:35]
  wire  M_Core_io_out_Clk_out; // @[PUF_Top.scala 16:35]
  wire  M_Core_io_out_Clk; // @[PUF_Top.scala 16:35]
  wire  M_Clk_Divider_clk; // @[PUF_Top.scala 19:35]
  wire  M_Clk_Divider_rst_p; // @[PUF_Top.scala 19:35]
  wire  M_Clk_Divider_clk_div; // @[PUF_Top.scala 19:35]
  core M_Core ( // @[PUF_Top.scala 16:35]
    .clock(M_Core_clock),
    .reset(M_Core_reset),
    .io_out_Data_in(M_Core_io_out_Data_in),
    .io_out_Ena_in(M_Core_io_out_Ena_in),
    .io_out_Clk_in(M_Core_io_out_Clk_in),
    .io_out_Ena_out(M_Core_io_out_Ena_out),
    .io_out_Clk_out(M_Core_io_out_Clk_out),
    .io_out_Clk(M_Core_io_out_Clk)
  );
  clk_divider #(.NUM_DIV(100), .CNT_LEN(8)) M_Clk_Divider ( // @[PUF_Top.scala 19:35]
    .clk(M_Clk_Divider_clk),
    .rst_p(M_Clk_Divider_rst_p),
    .clk_div(M_Clk_Divider_clk_div)
  );
  assign io_out_Data_in = M_Core_io_out_Data_in; // @[PUF_Top.scala 25:21]
  assign io_out_Ena_in = M_Core_io_out_Ena_in; // @[PUF_Top.scala 25:21]
  assign io_out_Clk_in = M_Core_io_out_Clk_in; // @[PUF_Top.scala 25:21]
  assign io_out_Ena_out = M_Core_io_out_Ena_out; // @[PUF_Top.scala 25:21]
  assign io_out_Clk_out = M_Core_io_out_Clk_out; // @[PUF_Top.scala 25:21]
  assign io_out_Clk = M_Core_io_out_Clk; // @[PUF_Top.scala 25:21]
  assign M_Core_clock = M_Clk_Divider_clk_div; // @[PUF_Top.scala 18:33 PUF_Top.scala 22:29]
  assign M_Core_reset = reset;
  assign M_Clk_Divider_clk = clock; // @[PUF_Top.scala 20:29]
  assign M_Clk_Divider_rst_p = reset; // @[PUF_Top.scala 21:39]
endmodule
